產(chǎn)品內(nèi)容介紹
BASLER A403K工業(yè)相機
Camera Link是一種通信鏈路用于科學(xué)和工業(yè)領(lǐng)域的視覺應(yīng)用。Camera Link于2000年由Basler和機器視覺領(lǐng)域的其他領(lǐng)先公司成立。標(biāo)準(zhǔn)Camera Link支持每秒680 MB的最大數(shù)據(jù)傳輸速率，具體取決于配置。采集和評估數(shù)據(jù)的幀抓取器通常用于通過camera Link接口連接相機和PC。Camera Link提供的最重要的好處是：?視覺技術(shù)的公認(rèn)通信標(biāo)準(zhǔn)（攝像機幀抓取器）?簡單且標(biāo)準(zhǔn)化的電纜概念?特別適合高數(shù)據(jù)速率?用于多種類型數(shù)據(jù)傳輸?shù)臉?biāo)準(zhǔn)化數(shù)據(jù)協(xié)議，例如單/雙抽頭、8位、10位、RGB、，等?通過幀抓取器通信端口1與攝像機進行串行通信。使用帶溫度傳感器的模擬輸入模塊時，提供第九通道。在為AI模塊定義其他八個熱電偶點時，point Builder Instrumentation（點生成器儀表）選項卡的CJ Compensation（CJ補償）字段需要第九個點（有關(guān)更多信息，請參閱第8節(jié)）。2安裝在個性模塊位置的空腔插件（1C31238H01），為模塊提供接線示意圖標(biāo)簽。通常，此模塊類型不需要實際的個性模塊。3升高和降低回退輸入可以禁用，并用作用戶定義的輸入點。配置說明包含在套件1C31174G20中。
在第14節(jié)中添加以下更改
位0：該位配置模塊（寫入）或指示模塊的配置狀態(tài)（讀?。??！?”表示模塊已配置。位1：強制模塊進入錯誤狀態(tài)，點亮模塊的錯誤指示燈。位2-5：模塊未使用。位6-7：保留用于工廠測試，必須始終設(shè)置為0。位8：硬件錯誤。表示以下一項或多項為真：-FPGA在啟動時未正確編程。-EE內(nèi)存校驗和不正確-PROM校驗和測試失敗。-內(nèi)部內(nèi)存診斷失敗。如果模擬通道正常，則LED亮起。然后，如果HART消息交換正確發(fā)生，LED將閃爍100毫秒。如果模擬通道正常，并且模塊發(fā)送消息且未收到正確響應(yīng)，則LED將閃爍400毫秒。第22-2頁，在第22-2節(jié)（操作）第二段（雙通道…序列）后添加以下信息：從版本0C開始，RSR固件支持級聯(lián)PI配置，其中PI 1的輸出用作PI 2的目標(biāo)位置輸入。支持級聯(lián)操作的其他功能是選擇直接/間接PI操作的標(biāo)志，還有一個名為“撤退”的反收尾功能。這些新功能中的一些實際上獨立于級聯(lián)，但所有這些都在本文中詳細(xì)描述。第22-9頁，刪除校準(zhǔn)模式部分下完全校準(zhǔn)項目符號第二段（任意極限…10.0伏）后的所有剩余段落（六）：第22-9.頁，添加以下信息代替上述項目中刪除的段落：當(dāng)要求完全校準(zhǔn)時，閥門首先行程至0%。在0%時，解調(diào)器增益被調(diào)整，直到反饋電壓接近10伏。此時解調(diào)器增益是最大可能的解調(diào)器增益。然后閥移動到100%。如果電壓大于10伏或超出刻度，解調(diào)器增益將降低，并讀取電壓讀數(shù)。該讀數(shù)為100%標(biāo)定閥。然后，閥門移動至0%，并讀取電壓讀數(shù)。該讀數(shù)為0%校準(zhǔn)值。確定0%校準(zhǔn)閥后，新值寫入EE存儲器
Camera Link is a communication link
for visual applications in the fields of science and industry. Camera Link was founded in the year 2000 by Basler and other leading companies in the machine vision arena. Standard Camera Link enables a maximum data transmission rate of 680 MB per second depending on the configuration. Frame grabbers which collect and evaluate the data are usually used to connect the camera and the PC via the Camera Link interface. The most important benefits afforded by Camera Link are: ? Accepted communication standard for vision technologies (camera frame grabber) ? Simple and standardized cable concept ? Particular suitability for high data rates ? Standardized data protocol for several types of date transfer, for example single/dual tap, 8 bit, 10 bit, RGB, etc. ? Serial communication to the camera via the frame grabber communication port 1 A ninth channel is provided when using the Analog Input module with temperature sensor. This ninth point is needed for the CJ Compensation field of the Point Builder Instrumentation Tab when defining the eight other thermocouple points for the AI module (refer to Section 8) for additional information). 2 Cavity insert (1C31238H01) that fits into the Personality module position providing a wiring schematic label for the module. Typically, there is no actual Personality module required for this module type. 3 Raise and Lower Runback inputs can be disabled and used as user-defined input points. Configuration instructions are included in Kit 1C31174G20.
Add the Following Changes to Section 14
Bit 0: This bit configures the module (write) or indicates the configuration state of module (read). A “1” indicates that the module is configured. Bit 1: Forces the module into error state, illuminating the module’s Error LED. Bits 2-5: Not used by the module. Bits 6-7: Reserved for factory test, must always be set to 0. Bit 8: Hardware Error. Indicates one or more of the following are true: - The FPGA did not program correctly on startup. - The EE memory checksum is incorrect - The PROM checksum test has failed. - Internal memory diagnostic has failed.If the analog channel is healthy, the LED is illuminated. Then, if a HART message exchange occurs correctly, the LED is blinked off for 100 mSec. If the analog channel is healthy, and if the module sends a message and does not receive a correct response, the LED is blinked off for 400 mSec.Page 22-2, Add the following information after the second paragraph (The dual-channel...sequence.) in Section 22-2 (Operation): Starting with revision 0C, RSR firmware supports a cascaded PI configuration in which the output of PI 1 is used as the target position input for PI 2. Additional features to support cascading operation are flags to select direct/indirect PI operation, and an anti-windup feature called “retreat”. Some of these new features are actually independent of cascading, but all are described in detail in this document. Page 22-9, Delete all of the remaining paragraphs (six) after the second paragraph (Arbitrary limits...10.0 volts.) in the Full Calibration bullet under the Calibrate Mode Section: Page 22-9, Add the following information in place of the deleted paragraphs in above item: When full calibration is requested, the valve first travels to 0%. At 0%,demodulator gain is adjusted until the feedback voltage is near 10 volts. The demodulator gain at this point is the maximum possible demodulator gain. Then the valve travels to 100%. If the voltage is greater than 10 volts, or off-scale, demodulator gain is reduced, and a reading of the voltage is taken. This reading is the 100% calibration valve. Then the valve travels to 0% and a voltage reading is taken. This reading is the 0% calibration value. After the 0% calibration valve is determined, the new values are written to EE memory
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